Circuit designs are getting larger and more complex at the 90 nanometer and smaller technology nodes. Because the time to market is shrinking with advancements in technology and product innovation, design teams struggle with meeting tight schedules and remaining under budget. Factoring in Intellectual Property (IP) co-development, a verification methodology that is able to service the criteria of a customer for both quality of results and turnaround time is desired. With IP co-development, not all building blocks for a System-On-a-Chip (SoC) design are available off-the-shelf during an SoC build and integration. As a result, an intelligent “waiver” mechanism for Design Rule Checks (DRCs) pertaining to the IP is often sought. The SoC designers have to integrate IP that is not DRC clean owing to various reasons. For example, the IP received by the SoC designers may lack layer-identifications and/or incomplete verification of the IP at the Graphic Data System II (GDSII) format level. As the IP is being co-developed, some aspects of the IP have not been fully developed and/or validated. Scheduling on the SoC design to make progress at the top (design) level remains a reality even though the IP building blocks are not fully in place. Furthermore, a dynamic nature of process rule specifications create problems, whereby the place and route (i.e., design implementation) systems cannot keep pace and verification does not happen until the very end of the development cycle.